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[PVS] HLDVT 2010: Call for Papers


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                                          Call for Papers


                                      HLDVT 2010

IEEE International High-Level Design, Validation and Test Workshop



                     Anaheim, California, June 10-12, 2010



HLDVT 2010 is the fifteenth in a series of annual workshops designed to bring together a community of researchers in the areas of design, validation, and test. The workshop revolves around a common theme of addressing the integration of multiple functions on-chip at higher levels of design abstraction, and the techniques and methodologies for modeling, analyzing, and validating such systems. In particular, the workshop has become a unique forum for researchers and practitioners to discuss the practical issues associated with simulation and validation of extremely large designs. 

The topics of interest include (but not limited to):

Simulation-Based Validation

Formal Verification

Design Abstraction & Behavioral Modeling

Error Trace Interpretation and Debugging

Hybrid SAT/BDD/ATPG Methods

On-Chip and Core-Based Testing

Test Generation for Defects, Design Errors, and Delay

Design/Synthesis for Test

Hardware/Software and Mixed-signal System Co-Validation

Emulation and Prototyping

Post-silicon Validation and Debug

Paper Submission: The Program Committee invites authors to submit papers not to exceed 8 pages (IEEE two-column conference format with 10pt minimum font size) describing original and unpublished work. Panels and special session proposals are also invited. All submissions must be made electronically in PDF format using the paper submission webpage: http://www.hldvt.com/submissions. Please ensure that all the required contact details are entered during online submission.

Paper Publication and Presenter Registration: The submission of a paper or panel proposal will be considered as evidence that upon acceptance, the author(s) will present their paper. For the papers to appear in the program and proceedings, required is at least one full workshop registration by an author before the submission of camera-ready version. IEEE reserves the right to exclude a paper from distribution (e.g., removal from IEEE Xplore) if the paper is not presented at the workshop. 

Submission deadline: March 7, 2010

Acceptance Notification: April 6, 2010

Final manuscript: April 19, 2010

Questions regarding paper submissions and the program may be addressed to the program chair: Zeljko Zilic, programchair@hldvt.com. Other questions may be addressed to the general chair: Prabhat Mishra, generalchair@hldvt.com. Additional pertinent information will be made available at http://www.hldvt.com/10/.

Organizing Committee

General Chair

Prabhat Mishra, Univ. of Florida

Program Chair

Zeljko Zilic, McGill University

Past Chair

Priyank Kalla, Univ. of Utah

Finance Chair

Hao Zheng, Univ. of South Florida

Publications Chair

Miroslav Velev, Aries Design Automation

Web Publicity Chair

Ismet Bayraktaroglu, Sun

Publicity Chair

Shireesh Verma, Conexant

Local Arrangements Chair

Ian Harris, UC Irvine

Industry Liaison

Shankar Hemmady, Synopsys

Panel/Special Session Chair

Sandeep Shukla, Virginia Tech

Program Committee

Samar Abdi, Concordia Univ.

Valeria Bertacco, Univ. of Michigan

Marc Boul´e, ´ Ecole de Tech. Sup´erieure

Ed Cerny, Synopsys

Pankaj Chauhan, Calypto

Tim Cheng, UC Santa Barbara

Franco Fummi, Univ. di Verona

John Hayes, Univ. of Michigan

Michael Hsiao, Virginia Tech

Alan Hu, Univ. British Columbia

Nicola Nicolici, McMaster Univ.

Priyadarsan Patra, Intel

Laurence Pierre, Univ. Grenoble

Wolfgang Rosenstiel, T¨ubingen Univ.

Pablo Sanchez, Univ. of Cantabria

Torsten Schober, IBM Germany

Li-C. Wang, UC Santa Barbara

Jin Yang, Intel

Avi Ziv, IBM


Steering Committee

Bernard Courtois, CMP-TIMA

Masahiro Fujita, Univ. of Tokyo

Prab Varma, Blue Pearl Software


HLDVT 2010 is sponsored by the IEEE Computer Society Test Technology Technical Council and the IEEE CS Design Automation Technical Committee.