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[PVS] 2nd CFP: IJES - Special Issue on: Reconfigurable andMulticore Embedded Systems

[Please accept our apologies if you receive multiple copies]

============================= Call for Papers ============================

                                 International Journal of Embedded
Systems (IJES)

                                                              Special Issue on

                                 Reconfigurable and Multicore Embedded Systems


General Information
With the progress and popularization of embedded system in the past
few years, efficiency, instead of functionalities has become an
important factor in measuring the value of embedded system.

How to efficiently use the limited resources in an embedded system to
obtain optimal performance has also become a very important issue.
Reconfigurable and multi-core architectures are

promising solutions to this issue. Compared to conventional hardware
which fixed functionalities, reconfigurable hardware has better
flexibility in using the limited resources in an embedded

system. For the same amount of computing resources, conventional
hardware can provide a single set of functionalities only. However,
reconfigurable hardware can reuse the same resources to

provide multiple sets of functionalities at different time points.
Developers of embedded systems can also use the reconfigurable
technology to satisfy system requirements such as small area, high

performance, and low power consumption. The reconfiguration technology
is especially suitable for implementing run-time systems such as
wireless sensor applications. In the conventional single

-core architecture, all loads of computation burdened the only core
and the performance is limited to a critical point. This limitation is
solved by the multi-core architecture. In the multi-core

architecture, all of the cores can share the loads to achieve load
balancing and improve the performance substantially by exploring the
parallelism of computations. Since adopting both

reconfigurability and multi-core architectures can achieve high
performance, how to integrate these two technologies to achieve much
higher performance is an attractive research issue. The

contribution of this special issue is to encourage researchers to
publish their experiences in reconfigurable computing technologies,
multi-core embedded systems, and the integration of the two

research areas.

This special issue follows the 2009 WoRMES workshop on the same topic,
but is open also to contributions that were not presented in it.
Topics include but are not limited toG

* Reconfigurable Hardware Architectures
* Runtime Resource Management of Reconfigurable Hardware
* Operating Systems for Reconfigurable Embedded Systems
* Application Design for Reconfigurable Embedded Systems
* Dynamic Partial Reconfiguration Techniques
* Programming Models for Reconfigurable Systems
* Multi-core Operating Systems and Scheduling
* Hardware Designs for Multi-core Architectures
* Multi-core Application Design
* Programming Models for Embedded Multi-core Architectures
* Reconfigurable Multi-core Architecture Design
* Reconfigurable Multi-core SoC Implementation

Submission Information
Prepare the paper with either MS-Word or LaTeX. The paper should be
submitted in the PDF format. Please refer the webpage:
for the detailed format of submitted paper.
To submit a paper, please send one copy attached to an e-mail with the
title "[IJES-SIoRMES] paper submission" to the guest editors or e-mail
your file to:

Important Dates
Submission deadline: November 20th, 2009

Authors Notification: December 31st, 2009

Final Manuscript Due:     January 21st, 2010

Expected publication date:      March, 2010

Guest Editors for the IJES Special Issue on Reconfigurable and
Multicore Embedded Systems
Dr. Pao-Ann Hsiung
Department of Computer Science and Information Engineering
National Chung Cheng University
168, University Road, Min-Hsiung, Chiayi,
Taiwan-62102, ROC.
e-mail: pahsiung@cs.ccu.edu.tw
web: http://www.cs.ccu.edu.tw/~pahsiung/

Chun-Hsien Lu
Department of Computer Science and Information Engineering
National Chung Cheng University
168, University Road, Min-Hsiung, Chiayi,
Taiwan-62102, ROC.
e-mail: lch96p@cs.ccu.edu.tw
web: http://www.cs.ccu.edu.tw/~lchs91u/lchs91u.htm