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[PVS] DATE 2009 Monday Tutorials - Call for Participation

Dear Colleagues,

I would like to bring your attention to the tutorials held at DATE 2009 
and in particular to tutorial D2 on
"Formal and Semi-formal Methods for Correctness and Robustness" 
given by Dominique Borrione (TIMA, France), Emmanuelle Ecrenaz-Tiphene 
(LIP6 Univ. Paris VI, France), Rolf Drechsler (Univ. of Bremen, 
Germany), and Goerschwin Fey (Univ. of Bremen, Germany).

Please find the call for participation enclosed below.

With kind regards,
Goerschwin Fey

DATE 2009 Monday Tutorials - Call for Participation

Date: Monday 20th April 2009

Location: Nice, France

Eleven pre-conference tutorials will be given on Monday.  Most of these 
tutorials include speakers from EDA and microelectronics industry as 
well as academic and research organisations. Three are full-day 
tutorials (A, B, and C). Eight are half-day tutorials, four to be given 
in the morning (D1, E1, F1, and G1) and four in the afternoon (D2, E2, 
F2, and G2). A participant should enrol for either one full-day tutorial 
or two half-day tutorials (one in the morning and one in the afternoon).
For enrolment in half-day tutorials, you can choose any combination of 
the morning and afternoon half-day tutorials. Combination of a full-day 
tutorial with a half-day tutorial is, however, not allowed.
Full information about the tutorials can be found on the web - 

A - System-Level Modelling, Analysis and Synthesis of Embedded 
Multi-Core Designs
B-  Energy Harvesting Systems: Principles, Modelling and Performance 
C- Correct-by-Construction Embedded Software Synthesis: Formal 
Frameworks, Methodologies, and Tools
D1 - New Developments and Trends in Networks on Chip
D2 - Formal and Semi-formal Methods for Correctness and Robustness
E1 - Low Power Design under Parameter Variations
E2 - 3D Integration - Opportunities, Challenges and Industry Readiness - 
Perspectives from Design, Manufacturing and EDA
F1- Cross-Layer Approaches to Designing Reliable Systems using 
Unreliable Components
F2 - Power Optimised Design Techniques for Modern FPGAs
G1 - Advanced Testing and Test Driven Self-Tuning of Mixed-Signal/RF 
Circuits and Systems
G2 - Reliability, Availability and Serviceability of Networks-on-Chip

For registration - http://www.date-conference.com/main/registration-09

Dr. Goerschwin Fey
Group of Computer Architecture
Faculty 3 - Mathematics and Computer Science
University of Bremen
Bibliotheksstr. 1
28359 Bremen

Phone: +49 421 218 63944
Fax:   +49 421 218 98 63944
Email: fey@informatik.uni-bremen.de
Web:   http://www.informatik.uni-bremen.de/agra