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                  DSD'2008 CALL FOR PAPERS
              Architectures, Methods and Tools
    University of Parma, Parma (Italy), 3-5, September,2008


- Submission of papers: March 3rd, 2008
- Notification of acceptance: May 5th, 2008
- Deadline for final version: June 9th, 2008


The Euromicro Conference on Digital System Design (DSD) addresses all
aspects of (embedded) digital and mixed hardware/software system
It is a discussion forum for researchers and engineers working on
state-of-the-art investigations, development, and applications.
It focuses on advanced system, design, and design automation concepts,
paradigms, methods and tools, as well as, modern implementation technologies
that enable effective and efficient development of high-quality (embedded)
systems for important and demanding applications in fields such as
(wireless) communication and networking; measurement and instrumentation;
health-care and medicine; military, space, avionic and automotive systems;
security; multi-media and ambient intelligence.


T1: Systems-on-a-chip/in-a-package: generic system platforms and
platform-based design; network on chip; multi-processors; system on
re-configurable chip; system FPGAs and structured ASICs; rapid prototyping;
asynchronous systems; power, energy, timing, predictability and other
quality issues; intellectual property, virtual components and design reuse.

T2: Programmable/re-configurable architectures: processor, communication,
memory and software architectures with focus on application specific and/or
embedded computing, co-processors; processing arrays; programmable fabrics;
embedded software; arithmetic, logic and special-operator units.

T3: System, hardware and embedded software specification, modeling and
verification: design languages; functional, structural and parametric
specification and modeling; simulation, emulation, prototyping, and testing
at the system, register-transfer, logic and physical levels; co-simulation
and co-verification.

T4: System, hardware and embedded software synthesis: system,
hardware/software and embedded software synthesis; behavioral,
register-transfer, logic and physical circuit synthesis; multi-objective
optimization observing power, performance, communication, interconnections,
layout, technology, reliability, robustness, security, testability and other
issues; (dynamic) management of computational resources, power, energy etc.;
design environments for embedded systems and re-configurable computing.

T5: Emerging technologies, system paradigms and design methodologies:
optical, bio, nano and quantum technologies and computing; self-organizing
and self-adapting (wireless) systems; wireless sensor networks; ambient
intelligence and augmented reality; ubiquitous, wearable and implanted
systems; deep sub-micron design issues.

T6: Applications of (embedded) digital systems with emphasis on demanding
and new applications in fields such as: (wireless) communication and
networking; measurement and instrumentation; health-care and medicine;
military, space, avionic and automotive systems; security; multi-media,
instrumentation and ambient intelligence; health-care and medicine;
military, space, avionic and automotive systems; security; multi-media and
ambient intelligence.


SS1:   Fault Tolerance in Digital System Design: It addresses all aspects
related to concepts, theory, implementations and applications of fault
tolerance principles in digital systems design.
Special Session Organizer: Z. Kotásek, Brno U. of Technology (CZ)

SS2:   Prospective aspects of Networks-on-Chip: It addresses all aspects
related to concepts, implementations and applications of networks-on-chip as
well as related EDA tools. Nonetheless, its focus is on prospective issues
and interdisciplinary topics like reliability, system control, design flow,
application studies and the outlook on future developments in NOC design.
Special Session Organizer: C. Cornelius, Univ. of Rostock (DE)

SS3: Dependability and Testing of Digital Systems: It addresses emerging
issues, hot problems, new solution methods and their hardware and software
implementations in all fields of digital and mixed-signal system
dependability and testing. It it especially focused on the dependability and
testing related to the SoC technology and modern embedded applications.
Special Session Organizer: H. Kubátová, CTU in Prague (CZ)

SS4: Planning and Optimization of Sensor Network Systems: It aims at
contributions regarding both the architectural optimization of wireless
sensor networks and the off-line planning of the overall sensing
Special Session Organizer: W. Fornaciari, Politecnico Milano (I)

SS5: System-Level Energy Optimization of Embedded Software: It aims at
gathering within the same forum contributions regarding the optimization of
the energy at different abstraction levels: from the design of code up to
the library and task/resource management carried out at the operating system
Special Session Organizer: E. Villar,  Universidad de Cantabria (ES)

SS6: NEWCOM++: Flexible Radio Digital Design: It addresses all aspects
regarding both the architectural concepts and methodologies of
multi-standard, multi-mode flexible radios. Tradeoffs considering
flexibility vs. computational, power consumption parameters are cornerstones
of architecture selection.
Special Session Organizer: D. Noguet, CEA-LETI (FR)

More information: http://dsd08.iet.unipi.it/specialsessions.htm


The Conference Proceedings will be published by IEEE Computer Society
Press and they are widely available through the IEEE Xplore Digital Library.


Regular Papers: Submissions can be made that describe innovative work in the
scope of the Conference, and especially, in any of the above main areas of
interest (please indicate the topic area and the special session number).
Prospective authors are encouraged to submit their manuscripts for review
electronically through the following web page
(http://www.conftool.net/dsd2008/) or by sending the paper to the Program
Chair via email l.fanucci@dsd08.iet.unipi.it (only in the case of the web
access problem) before the deadline for submission.
Each manuscript should include the complete paper text, all illustrations,
and references. The manuscript should conform to the required format
single-spaced, double column, A4/US letter page size, 10-point size Times
Roman font, up to 8 pages.
In order to conduct a blind review, no indication of the authors' names
should appear in the submitted manuscript.

Case Study and Application Papers: Submissions can be made which report on
state-of-the-art digital systems, design methods and/or tools, and
(embedded) applications. Papers discussing lessons learned from practical
experience, demanding or new applications, and experimental research are
particularly encouraged. Manuscripts may be submitted in the same way as
regular papers.

Prospective authors should check that the following information are included
and guidelines followed while submitting the papers for refereeing purpose.

- The paper and its title page should not contain the name(s) of  the
  author(s), or their affiliation

- The first page of the paper should have the following information:
   (Title of the paper, Brief Abstract of the paper, Track Area,
   Conference topic area (write the most appropriate topic area),
   Up to six keywords)


Chairman: Lech Józwiak, Eindhoven U. of Tech. (NL)
Krzysztof Kuchcinski, Lund U. (SE)
Antonio Nunez, U. Las Palmas (ES)

Luca Fanucci  U. of  Pisa (IT)

Gianni Conte, U. of Parma (IT)
Giovanni Danese, U. of Pavia (IT)

Francesco Leporati, U. of Pavia (IT)
Monica Mordonini, U. of Parma (IT)


A.  Akkas, Koc U., (TK)
L. Benini, U. Bologna (IT)
P. Carballo, U. Las Palmas (ES)
C. Cornelius, Rostock U. (DE)
G. Danese, U. of  Pavia, (IT)
M. Danek, Cz. Ac. of Sci. (CZ)
R. Drechsler, U. of Bremen (DE)
N. Dutt, U. of Calif., Irvine (US)
P. Eles, Linköping U. (SE)
L. Fanucci  U. of  Pisa (IT)
E. Gramatová, Sl. Ac. of  Sci. (SK)
V. Hahanov, KNUR (UA)
M. Handy, Rostock U. (DE)
L. Józwiak, Eindhoven U. of Tech. (NL)
K. Judmann, Tech. U. of Vienna, (AT)
B. Juurlink, TU Delft, (NL)
S. Kaxiras, U. of Patras (GR)
K. Kent, U. Brunswick (CAN)
P. Kitsos, HOU Patras (GR)
O. Koufopavlou, U. Patras (GR)
H. Kubatova, Cz. TU. in Prague (CZ)
K. Kuchcinski, Lund U. (SE)
S. Kumar Jonkoping Univ. SE
M. Kuwahara, Toshiba Corp. (JP)
F. Leporati, U. of Pavia (IT)
T. Luba, Warsaw U. of Tech. (PL)
H. Maehle,  U. of Luebeck (DE)
E. Martins, U. of Aveiro (PT)
J.S. Matos, Univ. Porto (PT)
V. Muthukumar, UNLV (US)
W. Najjar , UC , Riverside (US)
A. Nunez, U. of Las Palmas G.C. (ES)
A. Orailoglu, UC, San Diego (US)
A. Pawlak, ITE & SUT (PL)
M. Perkowski, Portland St. U. (US)
A. Postula, U. of Queensland (AU)
J. Rabaey, U. of California, Berkeley (US)
B. Rouzeyre, U. Montpellier II (FR)
S. Ruelke, IIS-FhG Dresden (DE)
T. Sasao, Kyushu Ins. of Tech. (JP)
J-P. Soininen, VTT Electronics (FI)
J. Sosnowski, Warsaw U. of Tech. (PL)
J. Tiberghien, Vrije Univ. Brussel (BE)
D. Timmerman, Rostock U. (DE)
M. F. Toro, U of Concepcion (CL)
R. Ubar, Tallinn Tech. U. (EE)
M. Valero, Pol. U. of Catalunya. (ES)
M. Velev, Reservoir Labs (US)
H.T. Vierhaus, Brandenburg U. Tech (DE)
S. Vitabile, U. Palermo (IT)
K. Waldschmidt, J.W. Goethe U. (DE)
C. Wolinski, IRISA, Rennes (FR)
H. Yasuura, Kyushu U. (JP)
A. Zemva, U. of Ljubljana (SI)